Clock signals may be used in electronic circuits to provide timing information. An important aspect of a clock signal in many applications is the clock duty cycle, which may be defined as the ratio of the time the clock pulse is at a high level to the clock period. For example, a clock signal that is high for forty percent of a clock cycle and low for sixty percent of the clock cycle has forty percent duty cycle.
Various circuits may be designed to handle different duty cycles and duty cycles with relatively significant margins of error. However, a fifty percent duty cycle offers advantages in many applications. For instance, a fifty percent duty cycle enables a half-rate (double-edge) clocking system. A half-rate clocking system advantageously eases circuit design constraints compared to those of a full-rate (single-edged) clocking system because it effectively doubles the clock rate without having to double the corresponding VCO frequency. In contrast, when a clock signal has a duty cycle other than fifty percent, the time interval between the rising and falling edges differ from the time interval between the falling and rising edges. Thus, only one transition edge per cycle can be utilized as a valid reference point.
In high-speed applications, for example, such as an analogue-to-digital converter (ADC) and a double-data-rate (DDR) SDRAM, the timings of the rising and falling edges of the clock signal are critical. High-speed circuits utilize each half-cycle to perform an operation. Domino logic, for instance, utilizes a first half cycle to precharge the domino node and the second half cycle to evaluate associated logic. As a result, deviations from a fifty percent duty cycle reduce the amount of time available to perform operations during one of the half-cycles.
Unfortunately, whether the duty cycle is fifty percent or some other percentage, the duty cycle may become distorted or degraded while distributing the clock signal to various circuits of a system such as a computer. For example, mismatches between pull-up and pull-down circuits of clock drivers often skew the clock signal. Furthermore, many other sources of signal distortion or degradation commonly affect the duty cycle such as parameter shifts during semiconductor processing, dimensional variations of printed circuit boards, mismatched line and/or input impedances, environmental conditions, and other common sources.
One solution, at least in terms of the fifty percent duty cycle, is to generate a clock signal with twice the frequency and divide the clock signal. However, generation of a clock signal with twice the desired frequency is difficult and expensive for high performance designs. Furthermore, generation of a clock signal with twice the desired frequency involves high power consumption.
Other solutions involve integration of a duty cycle correction (DCC) circuit. Conventional DCC circuits are based upon the analogue method in which the difference of the duty cycle from fifty percent is averaged over time and is stored as a voltage level in a capacitor. However, the delay between rising and falling edges cannot be maintained at a constant value so the phase information for the clock signal is lost.
More recent innovations in DCC circuits rely on matching devices or external references to monitor the duty cycle of the clock signal. However, use of matching devices such as matched integrators or an external reference is problematic, especially considering that many of the sources of error for the duty cycle relate to errors in the design and/or manufacture of circuits.